The Presentation of a Low Noise UWB Amplifier Using an Inverter with Inductive Peaking Technique

Document Type : Original Article

Authors

1 Assistant Professor, Qom University of Technology, Qom, Iran

2 Assistant Professor, Department of Telecommunications and Electronics, Faculty of Electrical and Computer Engineering, Qom University of Technology, Qom, Iran

3 M.Sc., Qom University of Technology, Qom, Iran

Abstract

In this paper, a 3.1 to 10.6 GHz low noise amplifier is designed using the 130 nm CMOS technology. In this circuit, the source degeneration technique is employed to increase the bandwidth and achieve input impedance matching. In addition, a current reuse technique is employed to achieve a high gain. Since most output impedance matching techniques degrade the gain or linearity, an inverter along with an inductive peaking technique is used to provide the output impedance matching of 50 ohms and to improve both the linearity and gain. This technique enhances the third harmonic behavior and increases the gain by 2.7 dB. The proposed circuit achieves S11 of less than - 9.1dB, S22 of less than -10 dB, the maximum gain of 19.7 dB, NF of 2 to 2.7 dB, and IIP3 of -3.5 dBm. Moreover, the power consumption of the proposed circuit is 28 mw and the core layout size is 991.84 μm×701.4 μm. The advantages of the proposed circuit over UWB structures with the same technology are higher gain, lower noise figure (NF), and better output matching.

Keywords

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References

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History

  • Receive Date: 01 September 2021
  • Revise Date: 05 March 2022
  • Accept Date: 19 January 2022

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